Review - Design and Characterization of Digital Gates based on CNTFET and CMOS Technology

In this paper we review a procedure to design and characterize logic gates based on CNTFET and CMOS technology. For the first technology we use a CNTFET model, already proposed by us, while for the second one we use the BSIM4 model of the Advanced Design System (ADS) library. In particular we consider NAND and NOT gates at different supply voltages and frequencies, for both technologies. The optimal results, obtained using the simulator ADS, are at 0.5 V and 50 GHz for CNTFET, while for CMOS technology at 3 V and 200 MHz. Moreover we quantitatively show the comparison between the two considered technologies in term of delay and power delay product (PDP).