Improvement of the P/E window in nanocrystal memories by the use of high-k materials in the control dielectric

In this paper nanocrystals memories program curves are shown and their saturation points (steady state condition) can be observed. We present a model that relates the voltage shift at the steady state (Delta V-Tss) to the gate program voltage (V-G). Starting from a good agreement between experimental data and simulations for nanocrystals memory cells with a conventional dielectric structure (SiO2), we present the estimated values of the Delta V-Tss vs V-G for different control stacks. Our investigation shows an improvement if a material with a high dielectric constant and a small conduction band-offset with respect to the SiO2, is placed between two SiO2 layers when the first of them is very thin.