A fast near optimum VLSI implementation of FFT using residue number systems

Many FFT processor designs have been proposed, most of which have been limited by hardware costs when a large number of points is to be processed. In recent years, VLSI technology modified design methodology and determined a reduction of costs. The scope of this work is to present a fast near optimum VLSI architecture for solving an N-point FFT which exhibits T= ?(log log N) and AT²= (N²1og²N log log N). Main features are: very high parallelism, proper communication parallelism, residue arithmetic, table look-up techniques and pipeline of data. Moreover, it will be shown that design performance does not depend on the input and output data representation (residue or weighted notation).