Wide-band modelling of CMOS interconnections and voiding damages with the lumped element LE-FDTD method

This paper illustrates the application of a lumped element-finite difference time domain (LE-FDTD) simulator to the wide-band modelling of CMOS interconnections. To achieve very accurate results the short-open calibration (SOC) technique has been adopted. Specific parameters of a CMOS interconnection laterally screened by a stack of metal vias have been extracted in the two cases of an unperturbed and a purposely damaged metal line. The behaviour of void-like defects in the metal line has been also studied using the fully three-dimensional capabilities of the simulator. It has been demonstrated that, at least in the simulated cases, only the specific resistance is affected by damaging.