A SPICE MODEL OF THE PEO-PANI MEMRISTOR

The memristor is a novel circuit element which is capable of maintaining an activity-dependent nonvolatile resistance and is therefore a candidate for use in next-generation storage and logic circuits. In this article, we present a model of the PEO-PANI memristor for use in the SPICE circuit simulation program which is especially suited to analog logic applications. Two variants are presented herein; accompanying each is a short description that explains any design decisions made, as well as elucidating on preferred simulation settings. It is shown that the model accurately replicates corresponding experimental results found in the literature. Simple simulations are used to show the suitability of each variant to specific experimental usage. Appendices contain verbatim implementations of the SPICE models.