Effect of temperature-bias annealing on the hysteresis and subthreshold behavior of multilayer MoS2 transistors

The transfer characteristics (ID-VG) of multilayers MoS2 transistors with a SiO2/Si backgate and Ni source/drain contacts have been measured on as-prepared devices and after annealing at different temperatures (T-ann from 150 degrees C to 200 degrees C) under a positive bias ramp (V-G from 0 V to + 20 V). Larger T-ann resulted in a reduced hysteresis of the ID-VG curves (from similar to 11 V in the as-prepared sample to similar to 2.5 V after Tann at 200 degrees C). The field effect mobility (similar to 30 cm(2) V-1 s(-1)) remained almost unchanged after the annealing. On the contrary, the subthreshold characteristics changed from the common n-type behaviour in the as-prepared device to the appearance of a low current hole inversion branch after annealing. This latter effect indicates a modification of the Ni/MoS2 contact that can be explained by the formation of a low density of regions with reduced Schottky barrier height (SBH) for holes embedded in a background with low SBH for electrons. Furthermore, a temperature dependent analysis of the subthreshold characteristics revealed a reduction of the interface traps density from similar to 9 x 10(11) eV(-1) cm(-2) in the as-prepared device to similar to 2 x 1011 eV(-1) cm(-2) after the 200 degrees C temperature-bias annealing, which is consistent with the observed hysteresis reduction.Schematic representation of a back-gated multilayer MoS2 field effect transistor (left) and transfer characteristics (right) measured at 25 degrees C on an as-prepared device and after the temperature-bias annealing at 200 degrees C under a positive gate bias ramp from 0 V to + 20 V. (C) 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim