A VLSI binary multiplier using residue number systems

The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of an-bit multiplier. To perform multiplication using residue ari thmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconvert- ed to the original notation. It is shown that the proposed design requires an 2 area A=O(n log n) and an execution time 2 T=O(log n).