High-k materials in FLASH memories

The scaling down of Flash memories can be pursued using the conventional stacked gate architecture only with major changes of the active dielectrics, mainly the inter- poly dielectric (IPD). The necessity to reduce the writing/erasing voltages keeping satisfactory value for the capacitance coupling ratio ( ? g ) in order to guarantee an efficient voltage transfer from the control gate to the floating gate, brings to an aggressive reduction of the IPD EOT. Moreover, from the 45nm node, the IPD EOT should be further reduced, due to the loss of the contribution of the vertical sidewalls of the poly floating gate (fig.1). T