Hump characteristics and edge effects in polysilicon thin film transistors

Transfer characteristics of polycrystalline silicon (polysilicon) thin film transistors (TFTs) often show a "hump" in subthreshold regime. This effect, also observed in silicon-on-insulator (SOI) transistors, can be attributed to the presence of an enhanced electrical field at edges of the channel, which is related to the specific shape of the edge and its surrounding oxide. In this paper we attempt an analysis of the hump effect in polysilicon TFTs combining electrical measurements and two dimensional numerical simulations, and considering several geometries of the channel edge. The transfer characteristics showing the hump effect are analyzed in terms of a parallel of the main ("bulk") transistor with two parasitic transistors located at the channel edges. The main and parasitic transistors have different threshold voltages and subthreshold swings and the equivalent parallel circuit reproduces very well the experimental transfer characteristics. The effect on the hump of interface states and oxide fixed charge, localized at the edge regions, is also analyzed and it is found that a degradation of the edge interfaces can easily lead to a hump reduction, thus explaining the large variability in this effect observed for different devices and different processes.