Asynchronous modular systems

Systems constituted by interconnected asynchronus sequential circuits are examined, on the hypotheis that the reaction time of every circuit is unknown, and delays of arbitrary size are present on the interconnection wires. Three system propoerties are considerd, i.e. the well-driveness (the input state of every circuit changes only when the circuit is internally stable), the persistence (every signal is always absorbed by the unit to which it is directed) and the liveness (no situation is reached starting from which a signal is never sent in a given interconnection wire). An abstract model of a circuit and of a system is given in order to analyze the system propoerties. The synthesis problem is approached in terms of rules that allow us to obtain a larger system by interconnecting smaller ones, preserving the considered propoerties.