Study of CNTFETs as Memory Devices

In this paper we propose a procedure for the study of CNTFETs as memory devices. In particular we analyze the design of a 6-T SRAM, in order to evaluate the writing and reading times, in single and double supplies, the static noise margin, the static power consumption and the power-delay product. For these goals, we use a CNTFET model, already proposed by us. Then we apply the same procedure using the Stanford model in order to compare the obtained results. At last we apply the proposed analysis for the design of a 6-T SRAM in CMOS technology, showing the improvements obtained with CNTFET technology.