Majority and minority carrier traps in manganese as-implantated and post-implantation annealed 4H-SiC

Ion implantation of amphoteric impurities, like vanadium (V) or manganese (Mn), can be employed for the formation of resistive layers in 4H-SiC. Such layers can then be used for device isolation, in order to reduce the parasitic capacitance. While V implantation can form thermally stable resistive layers, not much is known on Mn implantation. In the present investigation, we electrically characterized Mn ion implanted samples by means of capacitance-voltage, deep level transient spectroscopy and current-voltage measurements. Two ion implantation schedules were carried out: single-energy and multiple-energy ions so to have gaussian and box-shaped Mn and related ion damage profiles, respectively. The former with a maximum concentration in the low 10^16 cm^-3 , the latter with a Mn plateaux of 10^17 cm^- 3 . It is found that several majority carrier traps, in the 0.4-1.7 eV range below the conduction band edge, and two minority carrier traps arise after implantation and after post-implantation annealing in the 1000-1800 °C temperature range. The detected traps, as well as previous reports in the literature, show that most of them can be associated to intrinsic defects. Box profile implanted layers show resistivity values in the 10^6 Ohm.cm after heat treatments of, at least, 1600 ° C.