A note on the VLSI counter

In this note, the area-time complexity of a VLSI counter is studied. Both a lower and an upper bound are derived which meet to within the exponent of the logarithmic factor. The proposed VLSI design derives from the parallel counter presented by Muller and Preparata, which requires O(log n) delay time and O(n) number of elements. An area of order n (log)^2 n will be shown to suffice for the VLSI network and a lower bound to (AT)^2 of order n log n will also be proved.