Impact of Technology on CNTFET-Based Circuits Performance

In this paper we present a study of the impact of technology on the CNTFET-based circuits performance. In particular we show the layout of a NOT gate, used as block to build a chain of NOT and a ring oscillator. Then we present the time domain simulations of these circuits in order to see how the parasitic elements could limit the high-speed performances of CNTFETs.