A measurement technique for thermoelectric power of CMOS layers at the wafer level

We propose a method aimed at executing accurate thermoelectric power measurements at the wafer level on micromachined test structures. In order to compensate for instrumental offsets and sensitivity limits typically existing in a standard wafer-level test instrumentation, a special purpose extraction technique is applied. The influence of air-convection and heating/cooling effects on the measurement is also discussed by carefully evaluating the results of finite-element simulations of heat exchange in the test structure. In order to validate the technique, test measurements on p and n-doped polysilicon layers are presented and compared with other results from the literature. Moreover, the accuracy of the measurement technique and its temperature resolution are discussed.