FPGA-based implementation of two-step schedulers for modular optical interconnection networks

Optical interconnection networks promise to overcome the limitations of current electronic switching fabrics, enabling higher throughput, lower latency, and lower power consumption. Multi-plane architectures, based on multiple optical switching domains (e.g., space, time, wavelength, orbital angular momentum), are gaining research attention because of their modularity and scalability compared to single-domain switches. An effective scheduler, namely, the two-step scheduler (TSS), has been proposed for multi-plane optical interconnection networks, exploiting their modularity to speed up computations while satisfying the peculiar scheduling constraints. In this paper, a hardware implementation of TSS for modular optical interconnection networks is presented and thoroughly assessed. Both scheduling steps are parallelized with the aim of optimizing the execution time. iSLIP and longest queue first (LQF) scheduling algorithms are exploited in each step, resulting in four TSS configurations that are compared among each other and with classical single-step schedulers (SSSs) in terms of scheduling and hardware performance. TSS outperforms SSS in terms of the number of iterations, maximum operating frequency, worst-case scheduling duration, and required logic resources (i.e., scalability) at the expense of a slight latency penalty. Among all TSS configurations, LQF-based TSS guarantees the lowest scheduling latency, while iSLIP-based TSS minimizes the scheduling duration and the use of field programmable gate array (FPGA) resources.