Advanced activation of ultra-shallow junctions using flash-assisted RTP

A key issue associated with the continuous reduction of dimensions of CMOS transistors is the realization of highly conductive, ultra-shallow junctions for source/drain extensions. Millisecond annealing as an equipment technology provides an ultra-sharp temperature peak of 1.6 ms width which favors dopant activation but nearly suppresses dopant diffusion to form extremely shallow, highly electrically-activated junctions without melting the substrate. On boron beamline implanted wafers the formation of junctions at peak temperatures ranging from 1275 up to 1325 oC was investigated. In the special case of boron, silicon wafers deeply pre-amorphized with Ge were also used. The thermal stability of these boron profile distributions was evaluated by subsequent thermal anneals ranging from 250 to 1050 oC with times from a few seconds to several hundred seconds. From these experiments the deactivation/re-activation mechanism for subsequent annealing can be explained. All the junctions were analyzed by four-point probe measurements; selected samples were analyzed by Hall-effect, secondary ion mass spectrometry (SIMS), and transmission electron microscopy (TEM)