Self-test of integrated circuit wafers

We propose a technique for performing the manufacturing test of integrated circuits in a wafer which consists in exercising all the chips with the same test sequence and in comparing the outputs of an appropriate set of chip pairs. The comparison outcomes are collected by a test computer, which uses this information to identify the good chips. Identification is correct under conditions which are very likely to hold and almost all good chips are very likely to be identified. Since the chips can be tested in parallel and the time to perform the identification algorithm is negligible. this approach greatly reduces the time needed to perform the manufacturing test. The role of the test computer is essentially limited to collecting and processing the comparison outcomes and the test can proceed at the maximum allowable speed of the circuits under test.