Charge Configuration Memory Devices: Energy Efficiency and Switching Speed

Current trends in data processing have given impetus for an intense search of new concepts of memory devices with emphasis on efficiency, speed, and scalability. A promising new approach to memory storage is based on resistance switching between charge-ordered domain states in the layered dichalcogenide 1T-TaS2. Here we investigate the energy efficiency scaling of such charge configuration memory (CCM) devices as a function of device size and data write time ?W as well as other parameters that have bearing on efficient device operation. We find that switching energy efficiency scales approximately linearly with both quantities over multiple decades, departing from linearity only when ?W approaches the 0.5 ps intrinsic switching limit. Compared to current state of the art memory devices, CCM devices are found to be much faster and significantly more energy efficient, demonstrated here with two-terminal switching using 2.2 fJ, 16 ps electrical pulses.