Defect-Tolerant Array Structures for VLSI and WSI Architectures

A redundant interconnection structure is introduced, which is suitable for being used to implement bi-dimensional arrays of processing elements, even in presence of faulty cells. It is intended for enhancing the yield of high density VLSI and WSI systems, by allowing to implement the bi-dimensional structures circumventing the defective parts. Theoretical bounds on the reconfiguration capabilities of the proposed structure are presented, and some practical consequences of them are illustrated. Then two different algorithms for structuring the circuit in presence of defective parts are introduced and their performance is evaluated by simulation results, in terms of probability of obtaining successful configurations.