Role of gate oxide thickness in controlling short channel effects in polycrystalline silicon thin film transistors

The drain bias induced threshold voltage variation in short channel (L=0.4 mu m) polycrystalline silicon thin-film transistors (TFTs), with different gate oxide thicknesses, is investigated with combined experimental measurements and numerical simulations. Drain-induced barrier lowering (DIBL) and floating body effects (FBEs), triggered by impact ionization, are the main causes of such variations. However, the effects are counterbalancing, with a reducing oxide thickness reducing DIBL, while, at the same time, increasing the relative impact of the FBE. Hence, drain bias induced threshold voltage changes, when normalized by oxide thickness, are independent of the gate oxide thickness in these TFTs.