A VLSI architecture for RNS with MI adders

Over several years, RNS applications were limited to addition, subtraction and multiplication with results expected within a predetermined range because of the absence of explicit information on number magnitude in the residue representation. Hybrid notations have been proposed to overcome this obstacle. In this paper, an architecture for adding and overflow checking is presented which is based upon Residue Number Systems with Magnitude Index (RNS with MI) and its area-time complexity is evaluated. It is shown that considerable execution time reduction may result for a wide class of applications at the cost of a slight increase of area cocupancy as compared with binary realizations. © 1991.