A model to improve analysis of CNTFET logic gates in verilog-A-part I: Static analysis

Academic Article
Publication Date:
2015
abstract:
In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.
Iris type:
01.01 Articolo in rivista
Keywords:
CNTFETs modelling; digital applications; noise margin; sub threshold currents
List of contributors:
Authors of the University:
Handle:
https://iris.cnr.it/handle/20.500.14243/424489
Published in:
CURRENT NANOSCIENCE (PRINT)
Journal