Transputer based Videocoders: Requirements and Architectures

Videocoding algorithms possess a high degree of computation concurrency that can be exploited by parallel architectures. This paper presents the status of an applied research aimed at the implementation of a Transputer based videocoder for professional workstations. Basic algorithms are reviewed in terms of computation requirements and the ones specifically developed for ATM systems up to 2Mbit/s are quantitatively analyzed. Architectural tradeoffs are presented so that the demonstrator architecture can be defined in its hardware and software aspects. A video transputer module is defined and designed down to the logical level. Different partitioning of the algorithm execution is possible using a newly proposed «Farmer» Operating System.