A fast near optimum VLSI implementation of FFT using residue number systems

Many FFT processor designs have been proposed, most of which have been limited by hardware costs when a large number of is to be processed. In recent years, VLSI technology modified design methodology and determined a general reduction of costs. The scope of this work is to present a fast near optimum VLSI architecture for solving an N-point 22 FFT which exhibits T= (loglogN) and = (N log N 10glogN). Main features are: very high parallelism. proper communication lelism, residue arithmetic, table lock-up techniques and pipeline of data. Moreover, it will be shown that design performance does not depend on the and output data representation (residue or weighted notation) .