Electrical properties of SiO2/SiC interfaces on 2°-off axis 4H-SiC epilayers

In this paper, the electrical properties of the SiO2/SiC interface on silicon carbide (4H-SiC) epilayers grown on 2°-off axis substrates were studied. After epilayer growth, chemical mechanical polishing (CMP) allowed to obtain an atomically flat surface with a roughness of 0.14 nm. Metal-oxide-semiconductor (MOS) capacitors, fabricated on this surface, showed an interface state density of ~1×1012 eV-1cm-2 below the conduction band, a value which is comparable to the standard 4°-off-axis material commonly used for 4H-SiC MOS-based device fabrication. Moreover, the Fowler-Nordheim and time-zero-dielectric breakdown analyses confirmed an almost ideal behavior of the interface. The results demonstrate the maturity of the 2°-off axis material for 4H-SiC MOSFET device fabrication.