A VLSI binary multiplier using residue number systems

The idea of performing multiplication of n-bit binary numbers using hardware based on residue number systems is considered. This paper develops a design of VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic 3 residue representation numbers are converted from binary to and result is reconverted to after the residue multiplications the original notation. It is seen that the proposed design requires an area A=O(n and an execution time T=O(log2 nJ .2 logn)