SiO2/SiC MOSFETs interface traps probed by nanoscale analyses and transient current and capacitance measurements

This paper aims to give an overview on some relevant aspects of the characterization of the SiO/4H-SiC interface, considering the properties of this system both at the interface and inside the insulator. Nanoscale scanning probe microscopy (SPM) techniques were used to get insights on the homogeneity of the SiO/SiC interface electrical properties upon metal-oxide-semiconductor (MOS) processing. On the other hand, capacitance and current measurements as a function of time were employed to investigate trapping states in MOS structures in the SiO/4H-SiC system. In particular, time-dependent gate current measurements gave information on the near interface oxide traps (NIOTs) present inside the SiO layer. The impact of the observed trapping phenomena on SiO/SiC metal oxide semiconductor field effect transistors (MOSFETs) operation is discussed.