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An efficient VLSI architecture for real-time additive synthesis of musical signals

Articolo
Data di Pubblicazione:
1999
Abstract:
This paper presents a new architecture for the hardware implementation of additive synthesis for high-quality musical sound generation. A marginally stable second-order infiniteimpulse- response filter is used to generate each sinusoid, the frequency, amplitude, and phase of which can independently be specified. A chip has been designed with a bit-level systolic array approach. It is capable of performing 1200 sinusoid real-time synthesis. Furthermore, it is possible to connect up to 11 chips, to achieve an outstanding 13 200 sinusoid synthesis. Two completely independent output channels are available as 20-b streams. The system is clocked at 60 MHz when working with a 44.1-kHz sampling rate. The integrated circuit is designed in a 0.5-m CMOS technology and has a core area of approximately 19 mm2.
Tipologia CRIS:
01.01 Articolo in rivista
Keywords:
Additive synthesis; Bit-level systolic arrays; IIR marginally stable filters; Musical synthesis algorithms; Real-time musical synthesis; Sinusoid generation; Systolic architectures
Elenco autori:
Bertini, Graziano
Link alla scheda completa:
https://iris.cnr.it/handle/20.500.14243/387929
Pubblicato in:
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Journal
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