Stack engineering of TANOS charge-trap flash memory cell using high-kappa ZrO(2) grown by ALD as charge trapping layer

ZrO(2) with a K value of 30 grown by atomic layer deposition has been integrated as charge trapping layer alternative to Si(3)N(4) in TANOS-like memory capacitors, with Al(2)O(3) as blocking oxide, SiO(2) as tunnel oxide and TaN metal gate. The fabricated device featuring 24 nm ZrO(2) exhibits efficient program and erase operations under Fowler-Nordheim tunneling when compared to a Si(3)N(4) based reference device with similar EOT and fabricated under the same process conditions. The effect of stack thermal budget (900-1030 degrees C range) on memory performance and reliability is investigated and correlated with physical analyses. Finally, scaling ZrO(2) down to 14 nm allows program and erase at lower voltages, even if the trapping efficiency and retention of these device need further improvements for the integration of ZrO(2) in next generation charge trapping nonvolatile memories.